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Browsing by Author Halavar, B.

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Showing results 1 to 6 of 6

Issue Date	Title	Author(s)	Supervisor(s)
2018	Accurate Performance Analysis of 3D Mesh Network on Chip Architectures	Halavar, B.; Talawar, B.	-
2018	Accurate Power and Latency Analysis of a Through-Silicon Via(TSV)	Pasupulety, U.; Halavar, B.; Talawar, B.	-
2019	Extending BookSim2.0 and HotSpot6.0 for power, performance and thermal evaluation of 3D NoC architectures	Halavar, B.; Pasupulety, U.; Talawar, B.	-
2018	Floorplan based performance evaluation of 3d variants of mesh and BFT networks-on-chip	Halavar, B.; Talawar, B.	-
2020	OP3DBFT: A power and performance optimal 3D BFT NoC architecture	Halavar, B.; Talawar, B.	-
2018	Thermal Aware Design for Through-Silicon Via (TSV) based 3D Network-on-Chip (NoC) Architectures	Pasupulety, U.; Halavar, B.; Talawar, B.	-

Showing results 1 to 6 of 6