Please use this identifier to cite or link to this item:
https://idr.l1.nitk.ac.in/jspui/handle/123456789/13478
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Veeranna, S.B. | - |
dc.contributor.author | Yaragatti, Udaykumar R. | - |
dc.contributor.author | Beig, A.R. | - |
dc.date.accessioned | 2020-03-31T08:45:59Z | - |
dc.date.available | 2020-03-31T08:45:59Z | - |
dc.date.issued | 2012 | - |
dc.identifier.citation | IET Power Electronics, 2012, Vol.5, 4, pp.493-500 | en_US |
dc.identifier.uri | https://idr.nitk.ac.in/jspui/handle/123456789/13478 | - |
dc.description.abstract | The main objective of the present work is to develop space vector-based synchronised bus-clamping pulse width modulation algorithms to improve total harmonic distortion and higher DC-bus utilisation of the three-level inverter in overmodulation region. The proposed algorithms can generate synchronised pulse width modulation waveforms with all possible pulse number preserving all the waveform symmetries. The results of the proposed algorithms are evaluated and compared with conventional space vector pulse width modulation algorithm. It is shown that the proposed algorithms give improved results in terms of total harmonic distortion and DC-bus utilisation than that of conventional one in overmodulation region. The proposed method is implemented and verified experimentally on a constant v/f drive fed from insulated gate bipolar transistor (IGBT)-based voltage source inverter using Motorola power PC-based embedded controller. 2012 The Institution of Engineering and Technology. | en_US |
dc.title | Space vector-based synchronised bus-clamping pulse width modulation algorithms for three-level voltage source inverter in overmodulation region | en_US |
dc.type | Article | en_US |
Appears in Collections: | 1. Journal Articles |
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.