Please use this identifier to cite or link to this item:
https://idr.l1.nitk.ac.in/jspui/handle/123456789/14712
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Krishna D.G.A. | |
dc.contributor.author | Karthikeyan A. | |
dc.date.accessioned | 2021-05-05T10:15:41Z | - |
dc.date.available | 2021-05-05T10:15:41Z | - |
dc.date.issued | 2020 | |
dc.identifier.citation | 2020 IEEE International Conference on Power Electronics, Smart Grid and Renewable Energy, PESGRE 2020 , Vol. , , p. - | en_US |
dc.identifier.uri | https://doi.org/10.1109/PESGRE45664.2020.9070625 | |
dc.identifier.uri | http://idr.nitk.ac.in/jspui/handle/123456789/14712 | - |
dc.description.abstract | This paper presents frequency feedback loop based Cascaded Delayed Signal Cancellation PLL employed for dynamic voltage restorer (DVR) application to compensate grid voltage disturbances. The primary and key function of PLL is continuous tracking of grid voltage angle in a precise manner and feed it to DVR control. The conventional CDSC-PLL performance during frequency variation is poor which affects the estimation of grid voltage angle and thereby leads to maloperation of DVR control. Thus in this paper FFL is added to the CDSC-PLL to adapt for frequency variations for effective operation of DVR control. The performance analysis of FFL based CDSC-PLL is presented for various disturbances. Finally, FFL based CDSC-PLL is incorporated in the 10 kV, DVR system and the simulation results of the system for different voltage disturbances by using MATLAB/SIMULINK. © 2020 IEEE. | en_US |
dc.title | Design and analysis of frequency adaptive CDSC-PLL for Dynamic Voltage Restorer during adverse grid conditions | en_US |
dc.type | Conference Paper | en_US |
Appears in Collections: | 2. Conference Papers |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.