Please use this identifier to cite or link to this item: https://idr.l1.nitk.ac.in/jspui/handle/123456789/14948
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dc.contributor.authorKulkarni A.
dc.contributor.authorIteesh V.A.
dc.contributor.authorSahith S.R.
dc.date.accessioned2021-05-05T10:16:03Z-
dc.date.available2021-05-05T10:16:03Z-
dc.date.issued2019
dc.identifier.citationProceedings - 2019 IEEE International Symposium on Smart Electronic Systems, iSES 2019 , Vol. , , p. 350 - 354en_US
dc.identifier.urihttps://doi.org/10.1109/iSES47678.2019.00087
dc.identifier.urihttp://idr.nitk.ac.in/jspui/handle/123456789/14948-
dc.description.abstractThis paper looks into the modelling and analysis of on-chip interconnects in the lower metal region of an Integrated Circuit (IC). A proposed π-interconnect model is quantitatively modelled and analysed and the delay time, td is used as a metric to measure performance change from ideal circuit simulations for varying interconnect lengths using a driver-load inverter pair. The π-model delay time performance is also compared with that of a layout of an driver-load inverter pair circuit and a 3-stage ring-oscillator circuit. The layout is generated using MOSIS SCMOS technology using ON Semiconductor C5 600nm device model with VDD = 5V. All modelling and analysis is done using open-source EDA tools and technology. © 2019 IEEE.en_US
dc.titleModelling and analysis of lower metal on-chip interconnects using physical fabrication parametersen_US
dc.typeConference Paperen_US
Appears in Collections:2. Conference Papers

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