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dc.contributor.authorSravani K.
dc.contributor.authorRao R.
dc.date.accessioned2021-05-05T10:26:53Z-
dc.date.available2021-05-05T10:26:53Z-
dc.date.issued2020
dc.identifier.citationInternational Journal of Circuit Theory and Applications , Vol. 48 , 8 , p. 1363 - 1370en_US
dc.identifier.urihttps://doi.org/10.1002/cta.2771
dc.identifier.urihttp://idr.nitk.ac.in/jspui/handle/123456789/15316-
dc.description.abstractThis work presents the design of an asynchronous digital finite impulse response (FIR) filter suitable for high-performance partial response maximum likelihood (PRML) read channel ICs. A high throughput, low latency FIR filter is the basic requirement for the equalization process in read channels. To achieve the enhancement in speed and reduction in latency of the FIR filter, its computational units are deeply pipelined using high-capacity hybrid (HC-hybrid) logic pipeline method. The designed FIR filter has been simulated using UMC-180 nm and UMC-65 nm technologies. Simulation results show that the asynchronous digital FIR filter can operate up to a throughput of 1.17 Giga items/s in 180 nm and 2.3 Giga items/s in 65 nm technology yet with the latency in the order of ns. © 2020 John Wiley & Sons, Ltd.en_US
dc.titleDesign of high throughput asynchronous FIR filter using gate level pipelined multipliers and addersen_US
dc.typeArticleen_US
Appears in Collections:1. Journal Articles

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