Please use this identifier to cite or link to this item: https://idr.l1.nitk.ac.in/jspui/handle/123456789/6846
Full metadata record
DC FieldValueLanguage
dc.contributor.authorSomayaji, B.J.
dc.contributor.authorBhat, M.S.
dc.date.accessioned2020-03-30T09:46:14Z-
dc.date.available2020-03-30T09:46:14Z-
dc.date.issued2017
dc.identifier.citationJournal of Low Power Electronics, 2017, Vol.13, 4, pp.669-677en_US
dc.identifier.urihttp://idr.nitk.ac.in/jspui/handle/123456789/6846-
dc.description.abstractThis paper presents the design of RESURF based non-conventionalDrain ExtendedMOS (DEMOS) and its parametric analysis. The work investigates the impact of three primary parameters relating to p-implant, namely implant placement distance, implant doping and implant thickness, on device performance and premature avalanche breakdown. To avoid undesirable implant-drain punch-through, a boundary of limits is proposed near drain. Further, the implant parameters are optimized to maximize the ratio of Breakdown Voltage (BVt) to ON-resistance (RON). A breakdown voltage of 21 V at a low RON of 2.5 k? was achieved for a device gate length of 250 nm and gate oxide thickness of 5 nm. Using the optimized device design, the RF/Analog performance parameters are extracted and evaluated to enhance the suitability of the device for high voltage I/O applications in Sub-micron RF-SoC. Copyright � 2017 American Scientific Publishers All rights reserved Printed in the United States of America.en_US
dc.titleTriple reduced surface field drain extended MOS device design and its RF performance evaluation for sub-micron RF SoC platformen_US
dc.typeBook chapteren_US
Appears in Collections:2. Conference Papers

Files in This Item:
There are no files associated with this item.


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.