Please use this identifier to cite or link to this item:
https://idr.l1.nitk.ac.in/jspui/handle/123456789/7055
Full metadata record
DC Field | Value | Language |
---|---|---|
dc.contributor.author | Sharma, B.S. | |
dc.contributor.author | Bhat, M.S. | |
dc.date.accessioned | 2020-03-30T09:58:27Z | - |
dc.date.available | 2020-03-30T09:58:27Z | - |
dc.date.issued | 2017 | |
dc.identifier.citation | Proceedings of 2017 International Conference on Innovations in Electronics, Signal Processing and Communication, IESC 2017, 2017, Vol., , pp.1-4 | en_US |
dc.identifier.uri | http://idr.nitk.ac.in/jspui/handle/123456789/7055 | - |
dc.description.abstract | Structures based on Indium Gallium Arsenide (InGaAs) have attracted a lot of interest in Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) technology recently. In this paper, a new nano-scale dual-gate MOSFET using In0.75 Ga0.25As is proposed. Multiple designs were simulated with different doping concentration in the source/drain region and the channel stop region to get an excellent Ion/Ioff. Since current in Metal-Oxide-Semiconductor (MOS) depends on the doping profile of the channel, a careful re-engineering of the channel would improve the MOSFET characteristics. Channel length, Lg of the proposed device is 20 nm which produces a significant amplification and supports large current due to wide channel interaction. Simulation of In0.75 Ga0.25 As MOSFET with Lg = 20 nm, gate-oxide thickness toxGate1 = toxGate2 = 2nm and a width Z = 1000nm, exhibits transconductance gm-max ? 293.626 ?S/?m, subthreshold slope SS ? 70 mV/decade and drain-induced-barrier-lowering DIBL = 41.66 mV/V. � 2017 IEEE. | en_US |
dc.title | A novel dual-gate nano-scale InGaAs transistor with modified substrate geometry | en_US |
dc.type | Book chapter | en_US |
Appears in Collections: | 2. Conference Papers |
Files in This Item:
There are no files associated with this item.
Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.