Please use this identifier to cite or link to this item: https://idr.l1.nitk.ac.in/jspui/handle/123456789/7090
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dc.contributor.authorLad, K.
dc.contributor.authorBhat, M.S.
dc.date.accessioned2020-03-30T09:58:29Z-
dc.date.available2020-03-30T09:58:29Z-
dc.date.issued2013
dc.identifier.citation2013 International Conference on Computer Communication and Informatics, ICCCI 2013, 2013, Vol., , pp.-en_US
dc.identifier.urihttp://idr.nitk.ac.in/jspui/handle/123456789/7090-
dc.description.abstractA 1-V 1-GS/s 6-bit low power flash ADC in 90 nm CMOS technology is presented. Proposed Flash ADC consists of reference generator, comparator array, 1-out-of N code generator, Fat tree encoder and output D-latches. This Flash ADC achieves 5.76 ENOB at Nyquist input frequency without calibration. The measured peak INL and DNL are 0.08LSB and 0.1LSB, respectively. The proposed ADC consumes 15.75 mW from 1V supply and yielding an energy efficiency of 0.291 pJ/conv while operating at 1 GS/s. � 2013 IEEE.en_US
dc.titleA 1-V 1-GS/s 6-bit low-power flash ADC in 90-nm CMOS with 15.75 mW power consumptionen_US
dc.typeBook chapteren_US
Appears in Collections:2. Conference Papers

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