Please use this identifier to cite or link to this item: https://idr.l1.nitk.ac.in/jspui/handle/123456789/7210
Full metadata record
DC FieldValueLanguage
dc.contributor.authorRamesh, Kini, M.-
dc.contributor.authorSumam, David S.-
dc.date.accessioned2020-03-30T09:58:38Z-
dc.date.available2020-03-30T09:58:38Z-
dc.date.issued2011-
dc.identifier.citationICCSP 2011 - 2011 International Conference on Communications and Signal Processing, 2011, Vol., , pp.112-116en_US
dc.identifier.urihttps://idr.nitk.ac.in/jspui/handle/123456789/7210-
dc.description.abstractPerformance of Signal Processing Algorithms implemented in hardware depend on efficiency of datapath, memory speed, and address computation. Pattern of data access in signal processing applications is complex and it is desirable to execute the innermost loop of a kernel every clock. This demands generation of typically three addresses per clock: two addresses for data sample/coefficient and one for storage of processed data. Presence of a set of dedicated, efficient Address Generator Units (AGU) helps in better utilization of the datapath elements by using them only for kernel operations; and will certainly enhance the performance. This paper focuses on design and implementation of Comprehensive Address Generator Unit (CAGU) for complex addressing modes required by DSP Kernels used in Multimedia Signal Processing. An 8 bit CAGU has been implemented using UMC 0.18 micron, 6 metal layers process, that occupies 21802 sq microns, consuming 2.95 mW and works with a clock period of 6 ns. � 2011 IEEE.en_US
dc.titleAddress generation for DSP Kernelsen_US
dc.typeBook chapteren_US
Appears in Collections:2. Conference Papers

Files in This Item:
File Description SizeFormat 
7210.pdf1.28 MBAdobe PDFThumbnail
View/Open


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.