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DC Field | Value | Language |
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dc.contributor.author | Mehra, H. | |
dc.contributor.author | Bhat, M.S. | |
dc.date.accessioned | 2020-03-30T10:18:11Z | - |
dc.date.available | 2020-03-30T10:18:11Z | - |
dc.date.issued | 2019 | |
dc.identifier.citation | 2018 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics, DISCOVER 2018 - Proceedings, 2019, Vol., , pp.163-168 | en_US |
dc.identifier.uri | http://idr.nitk.ac.in/jspui/handle/123456789/8193 | - |
dc.description.abstract | Due to increasing complexity of VLSI systems, design optimization at higher levels of abstraction is all the more important to derive maximum performance mileage. Retiming is a powerful sequential optimization technique used to move registers across the combinational logic or to optimize the number of registers to improve performance via power-delay trade-off, without changing the input-output behavior of the circuit. This paper presents a high-level technique to retime a given sequential circuit to achieve lower clock period and a lower register count and their trade-off. The techniques used in this paper include cutset retiming, retiming for clock period minimization and retiming for register minimization. An environment is created using MATLAB, which takes a non-retimed circuit in the form of a netlist and a retimed netlist is generated with reduced critical path and/or with reduced number of flip-flops, thereby improving the overall performance. � 2018 IEEE. | en_US |
dc.title | High Level Optimization Methodology for High Performance DSP Systems using Retiming Techniques | en_US |
dc.type | Book chapter | en_US |
Appears in Collections: | 2. Conference Papers |
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