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dc.contributor.authorDeshmukh, A.A.
dc.contributor.authorJothish, M.
dc.contributor.authorChandrasekaran, K.
dc.date.accessioned2020-03-30T10:22:32Z-
dc.date.available2020-03-30T10:22:32Z-
dc.date.issued2016
dc.identifier.citationProceedings of the 2015 International Conference on Applied and Theoretical Computing and Communication Technology, iCATccT 2015, 2016, Vol., , pp.33-38en_US
dc.identifier.urihttp://idr.nitk.ac.in/jspui/handle/123456789/8664-
dc.description.abstractCryptographic hash algorithms have gained widespread popularity over its algorithmic complexity and the impossibility of recreation of the original input from the message digest. Embedded systems employ such algorithms for its security after substantial modifications in order to meet the hardware specifications due to the parsimonious capacity of such systems. Efficacious hashing algorithms lucidly adhere to all performance constraints and therein lies its popularity. We propose an optimization of the Secure Hashing Algorithm 1 (SHA-1) in memory requirements to suit the environment of an embedded system. We explore the idea of simplifying SHA-1's complicated set of steps to quicken its execution through loop reduction and lookup buffers stored in the main memory. � 2015 IEEE.en_US
dc.titleOptimized cryptographic algorithm for embedded systemsen_US
dc.typeBook chapteren_US
Appears in Collections:2. Conference Papers

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