Please use this identifier to cite or link to this item: https://idr.l1.nitk.ac.in/jspui/handle/123456789/13184
Title: Synchronized symmetrical bus-clamping PWM strategies for three level inverter: Applications to low switching frequencies
Authors: Veeranna, S.B.
Yaragatti, Udaykumar R.
Beig, A.R.
Issue Date: 2011
Citation: International Journal of Emerging Electric Power Systems, 2011, Vol.12, 2, pp.-
Abstract: The digital control of three-level voltage source inverter fed high power high performance ac drives has recently become a popular in industrial applications. In order to control such drives, the pulse width modulation algorithm needs to be implemented in the controller. In this paper, synchronized symmetrical bus-clamping pulse width modulation strategies are presented. These strategies have some practical advantages such as reduced average switching frequency, easy digital implementation, reduced switching losses and improved output voltage quality compared to conventional space vector pulse width modulation strategies. The operation of three level inverter in linear region is extended to overmodulation region. The performance is analyzed in terms THD and fundamental output voltage waveforms and is compared with conventional space vector PWM strategies and found that switching losses can be minimized using bus-clamping strategy compared to conventional space vector strategy. The proposed method is implemented using Motorola Power PC 8240 processor and verified on a constant v/f induction motor drive fed from IGBT based inverter. 2011 Berkeley Electronic Press. All rights reserved.
URI: https://idr.nitk.ac.in/jspui/handle/123456789/13184
Appears in Collections:1. Journal Articles

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