Design of CMOS RF receiver front-end for IEEE 802.11b

Abstract

This paper presents the design of a fully integrated receiver front-end for a 2.4GHz RF transceiver. The proposed receiver front end (Low-Noise Amplifier and Mixer) is based on a direct conversion architecture designed in 0.18?m CMOS technology. The chip provides a down conversion gain to the 50 MHz IF of 13.2 dB, SSB Noise Figure (NF) of 7.65 dB and a 3rd-order input intercept point (IIP3) of -14.6dBm consuming 50.6mW at1.8 V. �2008 IEEE.