Please use this identifier to cite or link to this item: https://idr.l1.nitk.ac.in/jspui/handle/123456789/7667
Title: Design of high performance dual-gate nano-scale In0.55Ga0.45 as transistor with modified substrate geometry
Authors: Sharma, B.S.
Bhat, M.S.
Issue Date: 2017
Citation: 2017 IEEE 8th Annual Ubiquitous Computing, Electronics and Mobile Communication Conference, UEMCON 2017, 2017, Vol.2018-January, , pp.271-277
Abstract: Structures based on Indium Gallium Arsenide (InGaAs) have attracted a lot of attention in Metal Oxide Semiconductor Field Effect Transistor (MOSFET) technology, recently. In this paper, we investigate the performance of a nano scale dual-gate MOSFET using InGaAs, and propose the design of a high performance In0.55Ga0.45As transistor with modified substrate geometry. Impact of changing the mole-fraction 'x' in In1-xGaxAs on the device performance is observed. To achieve best performance, the device geometry, relative mole fraction of In & Ga, the doping concentration of source/drain region and channel stop implant are varied. Simulations are performed to obtain output and transfer characteristics considering a N+ poly gate as well as a metallic (Al) gate for the proposed device. Simulations show excellent subthreshold slope (~ 62mV/dec), DIBL (~ 30 m V/V) and ION/IOFF = 2.23 � 106 values. As an application, an inverter is designed using this device and its DC and Transient responses for resistive and saturated enhancement NMOS load are plotted. � 2017 IEEE.
URI: http://idr.nitk.ac.in/jspui/handle/123456789/7667
Appears in Collections:2. Conference Papers

Files in This Item:
There are no files associated with this item.


Items in DSpace are protected by copyright, with all rights reserved, unless otherwise indicated.